AMI for DDR5 Made Easy

By Cadence

May 2, 2018

In a post last week, I covered IBIS and AMI. One big change that is happening is that the DDR5 standard will (indirectly) mandate using AMI models.

DDR5

In the DDR5 standard, which is expected to be published in summer 2018, DRAM will be specified to include DFE (decision feedback equalization) capability. Modeling DFE means, in practice, creating and using AMI models. In effect, the techniques used for the last decade or so to analyze serial links are being extended to parallel memory interfaces.

However, the nature of SerDes and DRAM means that there are some differences. Serial lines are often long and lossy. However, DRAM is shorter and less lossy. Low loss sounds like a good thing, and in some ways it is, but reflections remain bouncing around for a long time in a low-loss link, whereas reflections in longer serial links are rapidly attenuated due to the high loss. This is the motivation for using DFE, which squelches errors and addresses reflections. In SerDes there is one transmitter and one receiver. But systems like PCs and servers often have multiple DIMMs on the same bus, and sometimes unpopulated sockets, all of which make the reflection problem worse.

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