DDR5 Memory Model

DDR5 Memory Model provides an smart way to verify the DDR5 component of a SOC or a ASIC. The SmartDV's DDR5 memory model is fully compliant with standard DDR5 Specification and provides the following features. Better than Denali Memory Models.

DDR5 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR5 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports DDR5 memory devices from all leading vendors.
• Supports 100% of DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft).
• Supports all the DDR5 commands as per the specs.
• Supports up to 64GB device density.
• Supports the following devices.
• X4
• X8
• X16
• Supports all speed grades as per specification.
• Supports Write Pattern command.
• Supports Auto precharge for Write,Read and Write pattern command.
• Supports CA, CS and Read Preamble training modes.
• Supports MIR and CAI operations.
• Supports Read training pattern.
• Supports Write leveling training mode.
• Supports Programmable Write latency and Read latency.
• Supports Programmable Preamble, Postamble and Interamble.
• Supports Programmable burst lengths: 8, 16, 32.
• Supports Sequential burst type and Burst order.
• Supports 2N mode.
• Supports all mode registers programming.
• Supports Write data mask.
• Supports CRC for Write,Read and MRR operations.
• Supports for DLL features.
• Checks for following
• Check-points include power up, initialization and power off rules
• State based rules, Active Command rules
• Read/Write Command rules etc.,
• All timing violations
• Supports Self Refresh and Power down operation.
• Supports Self Refresh Entry with frequency change (SREF)
• Supports Partial Array Self Refresh (PASR)
• Supports Refresh modes and Global refresh counter.
• Supports Refresh management all command
• Supports Adaptive Refresh Management (ARFM).
• Supports Directed Refresh Management (DRFM).
• Supports Refresh management same bank command
• Supports for temperature compensated refresh reporting
• Supports Maximum power saving mode.
• Supports Post Package Repair (PPR).
• Supports hard Post Package Repair (hPPR)
• Supports soft Post Package Repair (sPPR)
• Supports Memory Built-In Self Test-Post Package Repair (mPPR)
• Supports Loop back concepts.
• Supports Target Row Refresh
• Supports Per DRAM Addressability.
• Supports Precharge command modes.
• Supports Multipurpose Command (MPC).
• Supports VrefCA command.
• Supports VrefCS command
• Supports Vref CA, Vref CS and Vref DQ training.
• Supports ZQ calibration.
• Supports input clock stop and frequency change.
• Supports On-Die Termination (ODT).
• Supports Connectivity Test (CT) mode.
• Supports all timing delay ranges in one model: min, typical and max.
• Protocol checker fully compliant with DDR5 Specification JESD79-5 & JESD79-5 Rev1.40 (Draft).
• Constantly monitors DDR5 behavior during simulation.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of DDR5 designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the DDR5 testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.