Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC
Last week, Cadence announced the certification of its LPDDR4 IP in TSMC's 16nm automotive process. The opening paragraph of the press release actually says:
"Cadence Design Systems, Inc today announced that the Cadence LPDDR4/4X memory IP subsystem, utilizing the TSMC 16nm FinFET Compact (16FFC) automotive process technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for ADAS and L3/L4 autonomous driving applications."
That's a lot of jargon in a few lines. Let me unpack it.
To read the full article, click here
Related Semiconductor IP
- DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
- Simulation VIP for LPDDR4
- LPDDR4 Synthesizable Transactor
- LPDDR4 DFI Synthesizable Transactor
- LPDDR4 Memory Model
Related Blogs
- GDDR7: The Ideal Memory Solution in AI Inference
- Flow Control Credit Updates in PCIe 6.1 ECN
- HBM4 Boosts Memory Performance for AI Training
- LPDDR6: A New Standard and Memory Choice for AI Data Center Applications
Latest Blogs
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA
- Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments