Cadence Memory IP for LPDDR4 Certified in TSMC 16FFC
April 23, 2019
Last week, Cadence announced the certification of its LPDDR4 IP in TSMC's 16nm automotive process. The opening paragraph of the press release actually says:
"Cadence Design Systems, Inc today announced that the Cadence LPDDR4/4X memory IP subsystem, utilizing the TSMC 16nm FinFET Compact (16FFC) automotive process technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for ADAS and L3/L4 autonomous driving applications."
That's a lot of jargon in a few lines. Let me unpack it.
To read the full article, click here
Related Semiconductor IP
- LPDDR4 Memory Model
- LPDDR4 DFI Verification IP
- LPDDR4 Synthesizable Transactor
- LPDDR4 DFI Synthesizable Transactor
- LPDDR4 Controller IIP
Related Blogs
- The Next-Generation UCIe IP Subsystem for Advanced Package Designs
- Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs
- Scale-Up and Scale-Out IP for Optical Interconnect for Accelerated Computing
- The Memory Imperative for Next-Generation AI Accelerator SoCs
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space