Bringing MEMS and asynchronous logic into an SoC design flow
May 3, 2010
Two companies at the Embedded Systems Conference this week have similar objectives, but for very different technologies. Coventor, a vendor of CAD and analysis tools for creating MEMS devices, described a plan for bringing MEMS design into the standard CMOS SoC flow. And asynchronous logic design shop Tiempo showed a flow that facilitates development of large asynchronous blocks within a conventionally synchronous SoC.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- Inventors & IP Management: Bill Meade Interview
- Lead Times Up, Inventories Low, Double-Ordering Rife, Capacity Strained
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space