Cadence at CES 2015: The IP Story
LAS VEGAS—The annual International Consumer Electronics Show (CES) here is not just about amazing new technologies, although that's what captures the public's attention. It's about the electronics design ecosystem that enables those products.
The Cadence meeting suite may traditionally be tucked away from the crowds near the back of South Hall 2, but it's no less a hive of activity involving members of the IP Group and partners and customers.
Martin Lund, senior vice president for Cadence's IP Group, took some time to talk during CES about what he saw on the show floor and in the bustling Cadence booth, where, he argued, some of the more amazing demos could be seen:
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- The Next-Generation UCIe IP Subsystem for Advanced Package Designs
- Cadence at CES 2015: Experience Integrated Solutions for Mobile
- Show report: CES 2015
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car