Big Innovations Double the Data Rate to 64 GT/s with PCIe 6.0
PCI Express® (PCIe®) has been on a tear, doubling the data rate with each new generation in response to the torrid rise in data traffic and the needs of advanced workloads. But raising signaling rates gets harder and harder with each doubling. That’s why with PCIe 6.0, we have some of the most dramatic changes yet seen in the standard to enable the jump to 64 GT/s.
First and foremost among the changes is the shift to PAM4 (“Pulse Amplitude Modulation with four levels”) signaling. PAM4 combines two bits per clock cycle for four amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ modulation with one bit per clock cycle and two amplitude levels (0, 1).
There are always tradeoffs, however, and the transition to PAM4 signal encoding introduces a significantly higher Bit Error Rate (BER) vs. NRZ. This prompted the adoption of a Forward Error Correction (FEC) mechanism to mitigate the higher error rate inherent in PAM4. PCIe 6.0 adopts an FEC that is sufficiently lightweight to have minimal impact on latency.
To read the full article, click here
Related Semiconductor IP
- PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
- PCIe 6.0 Retimer Controller with CXL Support
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
- PCIe 6.0 (Gen6) Premium Controller
Related Blogs
- Boosting Data Center Performance to the Next Level with PCIe 6.0 & CXL 3.0
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- A Big Problem with Big Data
- PCIE 6.0 vs 5.0 - All you need to know
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era