Azure for Silicon Design with Cadence and TSMC
I used to live on the Cote d'Azur, which is what everyone else calls the French Riviera. The name comes from the blue color of the Mediterranean Sea, azur in French. In English, it is azure. But it is probably more well-known today as the name of Microsoft's Cloud business. Ironically, the dictionary definition of the color azure is "bright blue in color, like a cloudless sky."
At last week's TSMC OIP Ecosystem Forum, the invited keynote was by Kushagra Vaid of Microsoft titled Modernizing Silicon Development Using the Cloud. He also gave the invited keynote at CDNLive Silicon Valley in 2017. See my post Microsoft CDNLive Keynote: Cloudy with a Chance of Chips for what he said then. He is GM for Azure Infrastructure for Cloud+AI. Perhaps more importantly for this audience is that he spent a dozen years as a chip designer at Intel. As he said at the CDNLive keynote "I've used plenty of Cadence tools."
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet
- Bringing Silicon Agility to Life with eFPGA and Intel’s 18A Technology
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car