Arteris vs Sonics battle...Let's talk NoC architecture
The Network on Chip is a pretty recent concept. Let’s try to understand how it works. Anybody who has been involved in the Supercomputer design (like I was in the 80’s), knows that you need a “piece” between the multiple CPU and memory banks, at that time a “crossbar switch”. To make it outrageously simple, you want to interconnect the M blocks on the left side with the N blocks on the right side, to do so you create a switch made of MxN wires.
To read the full article, click here
Related Semiconductor IP
- UALink PHY + Controller
- General Purpose Low-Dropout (LDO) - TSMC
- Camera Post-Processing IP
- DC-DC Split-Pi Boost-Buck Converter
- Deep learning accelerator
Related Blogs
- Breaking Down the "Make vs. Buy" Barriers for IP
- 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
- From DIY To Advanced NoC Solutions: The Future Of MCU Design
- NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers
Latest Blogs
- UALink Under the Hood: Why Full-Stack Verification Wins
- How to design secure SoCs Part IV: Runtime Integrity Protection
- High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits
- NVMe 2.0 Explained: What’s New and Why It Matters
- Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training