ARM's Cortex-A7 and A15: A Performance Versus Power Consumption Optimization Scheme
Last month's edition of InsideDSP included the article "NVIDIA and Qualcomm ARM Up Against Competitors," which discussed (among other things) NVIDIA's upcoming five-core Kal-El (i.e. Tegra 3) SoC. Tegra 3 combines four ARM Cortex-A9 cores built out of conventional 40 nm transistors and a fifth Cortex-A9 constructed from low-leakage (albeit switching speed-limited) circuits. The fifth core will operate stand-alone in low-performance usage scenarios (including, ironically, during high definition video playback sessions, thanks to the chip's dedicated-function hardware resources).
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- Altera's Next-Generation FPGAs: Advanced Process Lithographies Lead to Performance, Power Consumption Efficiencies
- ARM vs Intel...Performance? Power? OS support? Or ubiquity?
- Technical Comparison: USB Power Delivery r1.0 vs r2.0
- Next-Gen Cadence Tensilica Vision Processor Core Claims Big Performance, Energy Consumption Gains
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions