AI Requires Tailored DRAM Solutions: Part 3
October 6, 2020
Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part two of this four-part series touched on multiple topics including how AI enables useful data processing, various types of AI silicon, and the evolving role of DRAM. This blog post (part three) takes a closer look at the impact of AI on specific hardware systems, training versus inference, and selecting the most appropriate memory for AI/ML applications.
To read the full article, click here
Related Semiconductor IP
- 1G to 100G Single-Port MACsec Engine
- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
- Fast NIST ESV certified, FIPS (SP800-90A/B/C) True Random Number Generator
- Programmable Root of Trust Family With DPA & Quantum Safe Cryptography
- AES XTS/GCM Accelerators
Related Blogs
- AI Requires Tailored DRAM Solutions: Part 1
- AI Requires Tailored DRAM Solutions: Part 2
- AI Requires Tailored DRAM Solutions: Part 4
- ST-Ericsson (Part 3): Continuing To Innovate
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing