AI Requires Tailored DRAM Solutions: Part 4
Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part three of this four-part series touched on a wide range of topics including the impact of AI on specific hardware systems, training versus inference, and selecting the most appropriate memory for AI/ML. This blog post (part four) takes a closer look at the evolution of HBM and GDDR6, as well as the design tradeoffs and challenges of the two memory types.
To read the full article, click here
Related Semiconductor IP
- 1G to 100G Single-Port MACsec Engine
- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
- Fast NIST ESV certified, FIPS (SP800-90A/B/C) True Random Number Generator
- Programmable Root of Trust Family With DPA & Quantum Safe Cryptography
- AES XTS/GCM Accelerators
Related Blogs
- AI Requires Tailored DRAM Solutions: Part 1
- AI Requires Tailored DRAM Solutions: Part 2
- AI Requires Tailored DRAM Solutions: Part 3
- Intel vs. ARM: In the Smartphone Era (Part 4)
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust