Revolutionizing Automotive Communication: Exploring CAN XL Bus IP and Arasan's CAN IP Portfolio
June 22, 2023
Expert Perspectives on Semiconductor IP and SoC Design Archive - Page 49 of 196
PCIe 6.0 Takes the Spotlight
June 22, 2023
FPGAs or ASICs - What Are Their Differences and Similarities and How to Use Them for Security?
June 21, 2023
Ethernet IP: Unlocking the Power of High-Speed Data Transfer
June 20, 2023
The need for a holistic approach to safety and security
June 20, 2023
Optimization of AI Performance of SoCs for AD/ADAS
June 19, 2023
How to Maximize PCIe 6.0's Advantages with End-to-End PCIe Design Solutions
June 19, 2023
Developing a customized RISC-V core for MEMS sensors
June 16, 2023
New Neural Processor Aids in Adding AI to Small, Low-Power Vision Processing Designs
June 15, 2023
Setting a Foundation for Security with ReRAM
June 15, 2023
Understanding USB IP and Its Role in SOC Integration
June 14, 2023
How Standards Are Unleashing the Power of DPUs for Cloud Computing
June 14, 2023
Synopsys and AMD Collaboration Achieves Significant Milestones for EDA Workloads
June 14, 2023
When tapas meet tech: Barcelona's RISC-V Summit feeds our appetite for innovation
June 13, 2023
Ethernet IP a game-changer for SOC (System-on-Chip) designers
June 12, 2023
Early, Accurate, and Faster Exploration and Debug of Worst-Case Design Failures with ML-Based Spectre FMC Analysis
June 9, 2023
Customer Spotlight: Viettel Accelerates Design of Its First 5G SoC with Synopsys ASIP Designer
June 9, 2023
Why Aerospace Semiconductor Designers Are Taking a Page from Their Automotive Friends
June 8, 2023
Ethernet Time-Sensitive Network (TSN): Synopsys Verification Solution for Complex TSN Specifications
June 7, 2023
Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes
June 7, 2023