EDPS: 3D ICs, part I
The second day (more like a half-day) of EDPS was devoted to 3D ICs. There was a lot of information, too much to summarize in a few hundred words. The keynote was by Riko Radojcic of Qualcomm, who has been a sort of one-man-band attempting to drive the EDA and manufacturing industries towards 3D. Of course it helps if you don't just have a sharp arrow but the wood of Qualcomm behind it. Curiously, though, Qualcomm themselves have been cautious in actually using 3D IC technology. Possibly they have done some test chips but I don't know of any parts that they have in production.
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