What will change on the road to 3D ICs?

By EETimes

May 31, 2012

3D-IC represents different benefits for different applications. It can be both a performance enhancer and a power reducer due to shorter, lower capacitance interconnect lines, for example when used to stack memory on logic. It can provide a smaller overall footprint for mobile apps like cell phones, and it can improve yield when multiple smaller die can be assembled in lieu of a large SoC during early process maturity. It also allows analog and digital IP to hit performance and integration targets without forcing implementation in a single process. Depending on the application targeted, the jury is still out about relative costs and reliability, but there expectations for improvement in the long run in these areas as well.

To read the full article, click here