Arteris IP FlexNoC Interconnect Licensed by Baidu for Kunlun AI Cloud Chips for Data Center
NoC interconnect IP optimizes dataflow for revolutionary Cloud-To-Edge artificial intelligence (AI) system-on-chip (SoC) architecture
CAMPBELL, Calif. – January 15, 2019 – Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Baidu has licensed Arteris IP FlexNoC Interconnect for use in its high-performance Kunlun AI cloud chip for data center.
Baidu Kunlun AI cloud chips are unique because they are architected to perform both AI training and inference, whether located in a datacenter or in “edge” devices like vehicles or consumer electronics.
“The Arteris FlexNoC interconnect IP helps us greatly by enabling not only high bandwidth on-chip communications but also load-balanced data traffic to off-chip memory, all while simplifying our backend timing closure,” said Jian Ouyang, Principal Architect at Baidu. “In addition, Arteris IP’s strong local support team has been a trusted partner in our AI chip development projects.”
“Arteris IP is thrilled that the highly-respected Baidu AI team has chosen us as their interconnect IP partner for their pioneering AI SoCs,” said K. Charles Janac, President and CEO of Arteris IP. “We look forward to a long cooperation with Baidu as they innovate new technologies for artificial intelligence and machine learning algorithm hardware acceleration.”
About Arteris IP
Arteris IP provides network-on-chip (NoC) interconnect IP to accelerate system-on-chip (SoC) semiconductor assembly for a wide range of applications from AI to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye, and Texas Instruments. Arteris IP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, the CodaCache standalone last level cache, and optional Resilience Package (ISO 26262 functional safety), FlexNoC AI Package, and PIANO automated timing closure capabilities. Customer results obtained by using Arteris IP products include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit www.arteris.com .
Related Semiconductor IP
- Universal Chiplet Interconnect Express(UCIe) VIP
- AXI Interconnect
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
- AMBA AXI5-Lite Interconnect Verification IP
- AMBA AXI5 Interconnect Verification IP
Related News
- Rambus Enhances Data Center and AI Protection with Next-Gen CryptoManager Security IP Solutions
- sureCore PowerMiser IP enables KU Leuven chip for AI applications to achieve dynamic power saving of greater than 40%
- Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution
- Skymizer Launches HyperThought: Build Your Own AI Chip with Skymizer’s LPU IP
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale