Serial ATA (SATA) is computer bus standard that have the primary function of transferring data between Host and mass storage devi…
USB 3.0 Gen1 / Gen2 Device Controller IP
We provide configurable and scalable USB 3.0 host/device/dual mode controller IP Core for a wide range of applications.
The so_ip_sata3_hctrl is a soft core implementation of SATA host controller as defined in the SATA Specification 3.2.
The so_ip_sata2_hctrl is a soft core implementation of SATA host controller as defined in the SATA specification 2.6.
The IntelliProp IPC-BL109A-RD SATA RAID Core is a hardware design block written in HDL that performs RAID 0 operations to provide…
SATA HOST CONTROLLER core is compliant with SATA version 3.5 specification.
This SATA 3 Controller IP enables fast and efficient connectivity for storage devices, supporting high-speed data transfer.
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass …
SAS Initiator, 12G, 4 Ports, 48 Gbps
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment…
32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
Extoll’s SerDes architecture is based on digital design elements and methodologies.
32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
Extoll’s SerDes architecture is based on digital design elements and methodologies.
32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
Extoll’s SerDes architecture is based on digital design elements and methodologies.
Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
The Serial ATA Host Controller IP Core provides an interface to highspeed serial link replacements for the parallel ATA attachmen…
SATA-IP core - File system management without CPU
SATA IP core compliant with the Serial ATA specification revision 3.0 and work on AMD UltraScale and 7-Series device.
PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
Serial ATA (SATA) PHY Transceiver IP
SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…
10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…