Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
This circuit uses Altera’s new Arria and Stratix 10 FPGAs with hardwired support for floating-point operations (IEEE754).
Single precision fixed-size streaming floating-point FFT
This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FF…
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance The Cadence® Tensilica® Vision Q8 DSP delivers up to 3.84 te…
Tensilica FloatingPoint KQ7/KQ8 DSPs
Super-high-performance DSPs specifically optimized for floating-point workload with exceptional PPA Cadence® Tensilica® FloatingP…
Tensilica FloatingPoint KP1/KP6 DSPs
High-performance DSPs designed for floating-point-centric processing with ultra-low energy and small area Cadence® Tensilica® Flo…
The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based D…
The MixedRadix FFT IP Core uses a modular combination of radix2, 3, 5, and 7 Fast Fourier Transform (FFT) pipelined engines to pr…
The Fast Fourier transform (FFT) Intel FPGA intellectual property (IP) core is a high-performance, parameterizable FFT processor.
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
Variable FFT (run time choice of FFT size)
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
Speedcore embedded FPGA (eFPGA) IP has brought the performance and flexibility of programmable logic to ASICs and SoCs.
The UltraLong FFT IP Core uses an efficient Fast Fourier Transform (FFT) algorithm to provide multimillion-point discrete transfo…
The transform computation is based on a new matrix formulation of the discreet Fourier transform1 (DFT) which decomposes it into …
LTE Single Carrier FFT Circuit
Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.