DDR2 SDRAM IP Listing

DDR2 interface provides full support for the DDR2 interface, compatible with JESD79-2F specification and DFI-version 2.0 or highe…

• DDR
• In Production
• Immediately

The DDR and DDR2 SDRAM Controller with ALTMEMPHY Intel FPGA Intellectual Property (IP) provides simplified interfaces to industry…

• DDR

The DDR and DDR2 SDRAM controllers handle the complex aspects of using DDR and DDR2 SDRAM—initializing the memory devices, managi…

• DDR

Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth.

• DDR
• In volume production silicon
• Now
• DDR1, DDR2, DDR

The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…

• DDR

DDR2 SDRAM Controller

• DDR
• now
• Supports industrial standar…

Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth.

• DDR

Maps AXI4 transactions coming from the MicroBlaze™ to the User Interface Block providing an industry-standard bus protocol interf…

• DDR
• March 2014

The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3 and DDR2 SDRAM memor…

• TSMC
• 40nm
• LP

Memory Interface is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs.

• Bus Fabric

The DEINTERLACER_MA IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at a…

• Video Processing

VeriSilicon SMIC 0.13μm SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing…

• SMIC
• 130nm
• G

DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/RVT Logic proc…

• UMC
• 110nm
• HS

It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller u…

• UMC
• 130nm
• HS

DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.11um HS/AE (AL Enhance…

• UMC
• 110nm
• HS

DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process.

• UMC
• 130nm
• HS

The VID_FRAME_BUFFER (VFB) IP Core is a high-speed multi-format video frame buffer that samples an input video stream and buffers…

• Video Processing

The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…

• CPU

The H264-HP-E core is an and self-contained ITU-T H.264 High profiles hardware encoder.

• Video Processing

The JPEG2K-E core is a still image and video encoder that implements Part 1 of the JPEG 2000 standard.

• Image Conversion
• Silicon Proven
• NOW
• ISO/IEC 15444-1