Video Frame Buffer IP Core Rev. 2.0

The VID_FRAME_BUFFER (VFB) IP Core is a high-speed multi-format video frame buffer that samples an input video stream and buffers it in an external memory. The VFB is capable of very high-speed operation achieving over 300 MHz on standard FPGA platforms.

The VFB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VFB will drop or 'skip' an input frame. Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated3. The result is a system that seamlessly adapts to the different frame rates at the input and output of the VFB.

The memory port is a generic 128-bit read/write interface that may be connected to a wide variety of memory types and memory controllers. Memory read/write requests are sent as a sequential linear burst that is optimized for transfers over synchronous memory.

By using a series of VFB IP Cores in parallel, multiple video-sources may be synchronized together.

• Synthesizable, technology independent IP Core for FPGA, ASIC or SoC
• Supplied as human readable VHDL (or Verilog) source code
• Output supports full flow control permitting output pixels to be stalled (or even whole frames if necessary)
• Supports any video resolution1
• Support for RGB or YCbCr pixel formats
• Includes frame skip and frame repeat functionality to compensate for different input and output frame rates
• Generic 128-bit external memory interface with configurable burst size
• Linear memory bursts minimise page-breaks in synchronous memory architectures
• Ideal for interfacing to all types of memory such as SRAM, SDRAM, DDR, DDR2, DDR3, DDR4 etc.
• Supports 300 MHz+ operation on basic FPGA devices

• Buffering video frames in external memory
• Real-time digital video applications
• Video genlock applications
• Adapting to different pixel-clock rates and frame rates
• Essential component in video processing pipelines