HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
The logic required to create and validate designs for diverse applications is provided by HDMI Transmitter (TX) IP solutions, whi…
HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
In addition to adhering to HDMI 2.0 and 1.4 specifications, IP solutions for HDMI Transmitter (TX) devices offer the essential lo…
HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
In addition to adhering to HDMI 2.0 and 1.4 specifications, IP solutions for HDMI Transmitter (TX) devices offer the essential lo…
HDMI 2.0 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
The HDMI 2.O Rx IP complies with version 2.0b of the HDMI specification and offers the full functionality of an HDMI receiver.
HDMI 2.0 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
This HDMI 2.O Rx IP complies with HDMI specification version 2.0b and offers a full HDMI receiver capability.
HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
IP solutions for HDMI Transmitter (TX) devices are compliant with HDMI 2.0 and 1.4 specifications and offer the essential logic t…
HDMI 2.0 Rx PHY & Controller IP, Silicon Proven in TSMC 12FFC
This HDMI 2.O Rx IP provides a HDMI receiver function and complies with HDMI specification version 2.0b.
HDMI 2.0 Receiver with MHL 2.0
IP
Video Scaler with 4K Up/Down/Cross Conversion (Interleaved/Quadrant)
The VSC-4KX-IQ is a high quality polyphase scaler for up/down/cross conversion between video formats up to 4K resolution.
UHD Image Signal Processing (ISP) Pipeline
The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital proc…
Image Signal Processing Pipeline IP core
ISPIDO is a well established collection of IP Cores, enabling high resolution image signal processing and calibration on heteroge…
High Dynamic Range (HDR) Pipeline
The logiHDR is an Ultra High Definition (UHD) HDR pipeline designed for digital processing and image quality enhancements of the …
ACAP HDR Image Signal Processing Framework
The ACAP HDR Image Signal Processing Framework is intended to showcase a logicBRICKS IP suite implementation of High-Dynamic Rang…
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency …
- Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency …