400G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
400G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…
Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HB…
14-bit 12.5MSPS SAR ADC - Tower 65nm
The A14B12p5M is a high-performance, low-power analog-to-digital converter (ADC) intellectual property (IP) block designed for ap…
Third-Generation 5G-Advanced Modem IP Platform
Ceva’s third-generation PentaG platform is a production-ready 5G- modem IP architecture that integrates baseband hardware, L1 PHY…
Ultra-Low-Power Temperature/Voltage Monitor
The ODT-TVM-ULP-001C-28HPCPT is an ultralow power temperature and voltage monitor designed in a 28nm standard CMOS process.
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-low area and energy cost
Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of a…
Early adopter version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters The JESD204E Contro…
A 32Gbps SerDes PHY in GlobalFoundries 22FDX withlow-jitter, half-rate tran mission, and a configurable CTLE-based receiver.
Analog I/O Library with a custom 12V ESD Solution IN GF 55nm
An Analog I/O Library in GlobalFoundries 55nm LPx-BCDlite technology This I/O library is a silicon-proven, flip-chip-optimized an…
Standard Cell Library in SkyWater 90nm
A low-leakage digital standard cell library for energy-efficient, long-lifecycle SoC designs in SkyWater 90nm CMOS.
The Neuchips eFuse Controller IP is a robust hardware solution designed to manage embedded fuse (eFuse) arrays.
32Gbps SerDes IP in TSMC 12nm FFC
The relentless demand for higher data throughput in data centers and high-performance computing (HPC) systems drives the need for…
32Gbps SerDes IP in TSMC 22nm ULP
The relentless demand for higher data throughput in data centers and high-performance computing (HPC) systems drives the need for…
1G BASE-T Ethernet Verification IP
The 1G BASE-T Ethernet Verification IP provides deliverables an effective & efficient way to verify the components interfacing wi…
DVBS2_DEMOD.vhd performs the demodulation based on three tracking loops: carrier tracking (for coherent demodulation), symbol tim…
Truechip's NoC Verification IP provides an efficient & effective way to verify the NoC DUT.
10-bit Pipeline ADC - Tower 180 nm
The A10B25M is an ultra low-power, high-performance analog to digital converter (ADC) intellectual property (IP) design block.
Chiplet SCA/FI protected RoT with Post-Quantum Security Heterogeneous chiplet-based architectures require a trusted hardware anch…