Third-Generation 5G-Advanced Modem IP Platform

Ceva’s third-generation PentaG platform is a production-ready 5G-Advanced modem IP architecture that integrates baseband hardware, L1 PHY software, and comprehensive verification assets into a single reusable subsystem.

Compared with the previous generation, the third-generation PentaG platform delivers substantial improvements in performance, scalability, and integration efficiency across both satellite and terrestrial deployments.

Built on a unified architecture, the platform scales seamlessly across SATCOM, IoT, and infrastructure-class applications.

With a silicon-proven, pre-validated modem subsystem, the third-generation PentaG platform accelerates time-to-silicon and significantly reduces development risk.

The Solution

The third-generation PentaG platform delivers a fully integrated modem IP solution combining optimized hardware accelerators, 5G baseband software, and a comprehensive verification environment.

Delivered as a validated modem subsystem rather than discrete IP blocks, it simplifies SoC integration while preserving programmability and extensibility.

Leveraging silicon-proven IP and a unified architecture, the platform reduces integration complexity, accelerates time-to-silicon, and mitigates development risk across satellite, IoT, and infrastructure-class products.

• Complete, scalable hardware IP and software modules for 5G and legacy LTE modems
• Employs Ceva-XC vector DSP and Ceva-BX2 scalar DSP cores and function-optimized hardware accelerators
• 5G PHY software for modulation, demodulation, standard 5G procedures,
• Support for NR, eMBB, 5G-IoT and URLLC modes
• Supported by System-C Virtual Platform Simulator and FPGA-based hardware emulation
• Reusable foundation to spawn multiple products while keeping a consistent architecture and validation toolchain.
• Includes optimized baseband subsystems, Ceva’s vector and scalar DSPs compute power, hardware accelerated data & control path
• Scale across performance & power envelopes for broad range of applications
• Extendable and upgradable for future 3GPP reassesses

Production-Ready Baseband Processing Subsystem

• Complete, operational RTL subsystem integrating existing and new IP
• Programmable and future-proof through Ceva DSP architecture

Optimized Performance and Efficiency

• High-throughput, low-latency design
• Power-efficient architecture with optimized clock and power domains

Reduced Technical Risk

• Silicon-proven IP and validated subsystem integration
• Enhanced testability, debug, and trace capabilities
• Integrated co-simulation environment supporting early validation

Faster Time-to-Market

• Simplified SoC integration
• Reduced development complexity
• Accelerated time-to-silicon and overall program execution

• Consumer IoT
• Automotive
• Industrial 
• Mobile
• PC