Vendor: FortifyIQ, Inc. Category: Root Of Trust

Chiplet RoT Secure Core

Chiplet SCA/FI protected RoT with Post-Quantum Security Heterogeneous chiplet-based architectures require a trusted hardware anch…

Overview

Chiplet SCA/FI protected RoT with Post-Quantum Security

Heterogeneous chiplet-based architectures require a trusted hardware anchor to ensure secure integration, firmware integrity, and device identity. FortifyIQ’s Chiplet RoT is a compact, energy-efficient security IP core designed specifically for chiplet ecosystems, enabling secure boot, attestation, and identity management across multi-die systems.

Powered by FortifyIQ’s proprietary cryptographic engine, the Chiplet RoT supports both classical and post-quantum algorithms while incorporating patented countermeasures against side-channel and fault injection attacks. Engineered for flexible die-to-die interfaces and optimized for chiplet interconnect standards, it provides certifiable, quantum-resistant security for next-generation modular SoCs.

Key features

  • Efficient Performance
  • SCA/FIA Protections
  • Flexible Interfaces
  • Security Certification Readiness

Applications

  • Secure Communications
  • Network Devices

What’s Included?

  • SystemVerilog source code or netlist
  • Testbench, input vectors, and expected results
  • Sample timing constraints, synthesis, and simulation scripts
  • Hardware Abstraction Layer (HAL) reference implementation
  • Integration, configuration, and usage manuals
  • Firmware code
  • Software library 
  • Security documentation

Specifications

Identity

Part Number
FIQ-RoT04B
Vendor
FortifyIQ, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

FortifyIQ, Inc.
HQ: USA
FortifyIQ develops HW security IP cores fortified against Side-Channel (SCA) and Fault Injection attacks (FIA), while preserving the original AES goals of speed, low latency, and low power usage. We also offer high-performance software libraries and EDA tools for pre- and post-silicon security assessment. Our core protection algorithm was tested rigorously, passing the Test Vector Leakage Assessment (TVLA) test at 1 billion traces, and was certified by a third-party Common Criteria lab. Our cores are fully synthesizable, eliminating the need for custom cells or special place & route handling. Being algorithm-based, they are technology-agnostic, ensuring compatibility and security across diverse platforms and devices. Secure IP Cores and SW libraries FortiCrypt: Our Advanced AES IP cores provide robust protection against SCA, FIA, (including Differential Power Analysis-DPA, and Statistically Ineffective Fault Attacks-SIFA), alongside high performance, low latency, low gate count, and low power usage. Purely mathematically-driven, these cores achieve a high maximum frequency, and one clock cycle per AES round. Our FortiCrypt high-performance software library can be used to protect security vulnerabilities in HW in unprotected field devices even though they are already deployed, by a simple software download. They are based on the same security proven algorithm (STORM) as our ultra-low power IP cores, and are silicon proven. They have extremely high performance. Even on a low-end 1.1 GHz ARM processor the performance is high enough for Ultra HD (3840×2160) video streaming. FortiMac: These HMAC SHA2 cores provide robust protection against SCA, DPA, FIA, and SIFA, are suitable for lightweight applications and are purely algorithmic and thus implementation-agnostic. Our products, including the software library, offer protection of HMAC SHA2, based on the threshold implementation approach, validated analytically and on physical devices. FortiPKA-RISC-V: A Public Key Algorithm coprocessor with modular multiplication and SCA and FIA protection that streamlines operations by eliminating Montgomery domain transformations, enhancing the coprocessor's performance and reducing area. FortiPKEx: A low-cost key exchanger for companies currently using preinstalled symmetric keys due to cost constraints, but are considering shifting to key exchange protocols based on asymmetric cryptography with built-in resistance to SCA and FIA. EDA Tools: Comprehensive pre-silicon and post-silicon security assessment tools, including TVLA charts that pinpoint vulnerabilities down to specific modules and gates, greatly simplifying security debugging against a spectrum of physical attacks, including SCA, DPA, FIA, and SIFA. This effectively moves the security assessment to the same stage as the functional assessment. These tools were instrumental in developing all our secure IP cores and software libraries.

Learn more about Root Of Trust IP core

Root of Trust: A Security Essential for Cyber Defense

Imagine a datacenter powering critical cloud services, silently compromised by a tampered chip inserted during manufacturing. In most cases, the malware would be practically impossible to remove and could persist across formats/reinstalls !

Why Hardware Root of Trust Needs Anti-Tampering Design

The hardware root of trust (HRoT) provides the trust base (root key), hardware identifier (UID), hardware unique key (HUK), and entropy required for the secure operation of the entire chip and therefore is often the focus of hacker attacks. If the design can’t effectively resist attacks, hackers can easily obtain the secrets of the entire chip. Attackers can use the secrets to crack identity authentication and data encryption and steal product design know-how, causing application security problems.

Frequently asked questions about Root of Trust IP cores

What is Chiplet RoT Secure Core?

Chiplet RoT Secure Core is a Root Of Trust IP core from FortifyIQ, Inc. listed on Semi IP Hub.

How should engineers evaluate this Root Of Trust?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Root Of Trust IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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