This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins.
- TSMC
- 3nm
- N3A
- Available on request
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
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This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins.
TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins.
TSMC 22nm 5V5 ESD Power Clamp – Low Leakage
This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins.
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This TSMC 12nm 2.5V ESD Power Clamp IP macro provides compact, low-leakage ESD protection for FinFET designs.
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 12nm 0V8 ESD Local Protection Low Cap
This TSMC 12nm 0.8V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.
SMIC 28nm 0V75 ESD Power Clamp
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
SMIC 28nm 0V75 ESD Local Clamp – Low Capacitance
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs.
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
Mobiveil’s ONFI/Toggle IP is a flexible and configurable design targeted for enterprise storage applications like SSD.
The TSMC 2nm 1.2V GPIO offers configurable I/O functionality with multi-voltage support, over-voltage tolerance (OVT), and high-speed or ultra-low-power modes.
Optimized for 3D Wafer-on-Wafer (WoW) integration, the controller supports ultra-wide interface.
Fully compliant to SWI3S Specification version 1.0
4/8-bit mixed-precision NPU IP
Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…
SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Silicon-proven ESD protection for GAA/nanosheet technologies
TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
Silicon-proven ESD protection for GAA/nanosheet technologies
The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps.
High-performance, deterministic hardware IP for real-time signal processing, control algorithms, and embedded AI acceleration.