PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE 4…
LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-o…
LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-o…
LPDDR4 multiPHY V2 in Samsung (14nm, 11nm, 10nm, 8nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-o…
TSMC CLN28HPC+ 2.4GSps Analog Front-End
The IGAAFET05A which contains ADCs, DACs and PLLs is an analog front-end (AFE) IP for RF applications.
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
10G-KR, XFI, PCIe 3.1/2.0/1.0, XAUI, QSGMII, SGMII, Gigabit Ethernet
MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.
IEEE 1588 Boundary, Slave And Master Clock
The IPC9010 utilizes IPClock’s IEEE 1588 v2 technology optimized for providing high quality frequency synchronization and Time of…
IEEE 1588 Boundary, Slave And Master Clock
The IPC9006 utilizes IPClock’s IEEE 1588 v2 technology optimized for providing high quality frequency synchronization and Time of…
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
Avalon Multi-port DDR2 Memory Controller
The Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in…
GLONASS/GPS/Galileo/BeiDou multisystem single-band 2-channel receiver RFIC
NT1021 is a single-chip dual-channel RF front-end consuming a very low power (47 mW typical at 2.1 V) and performing a simultaneo…
IBM 65nm 10SF Process 24-Bit Stereo Sigma-Delta ADC/DAC
The I65GV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifi…
802.15.4 (Zigbee, 6LoWPAN, RF4CE, ISM) PHY
The 802.15.4 Transceiver core supports the PHY layer for a range of wireless PAN standards including Zigbee®, 6LoWPAN, RF4CE and …
802.11 A/B/G/N Direct Conversion Transceiver
The 802.11 a/b/g/n direct conversion transceiver IP core supports OFDM, WLAN and ISM applications.
IBM 65nm Low Leakage Process 24 Bit Stereo Sigma-Delta ADC/DAC
The I65LPEV25_CODEC_04B integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplif…
The S13V33_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifier,…
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU,…