Vendor: Synopsys, Inc. Category: LPDDR

LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm)

The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-o…

Controller + PHY + 1 LPDDR4 TSMC 28nm Available on request View all specifications

Overview

The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR4, LPDDR3, DDR4, DDR3, and/or DDR3L SDRAM interfaces operating at up to 4,267 Mbps.
With multiple interfaces, the LPDDR4 multiPHY can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 or DDR3 SDRAMs.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR4 multiPHY is provided as hardened IP macrocells including a 4 slice Address/Command macrocell (ACX4), an 8-bit data macrocell (DBYTE) that includes DM/DBI and data strobes, and a master macrocell (MASTER) that includes the PLL used by the PHY. The macrocells include fully integrated I/Os and are easily assembled into a variety of configurations from a single 16-bit LPDDR4 PHY to a 72-bit DDR4 PHY. An RTL-based PHY utility block (PUB) with firmware-based training capabilities supports the GDSII-based PHY. In addition to training the interface after boot-
up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, and facilitates ATE testing and interface diagnostics. The LPDDR4 multiPHY includes a DFI
4.0 version 2 interface to the memory controller and can be combined with the Synopsys Enhanced Universal Memory or Protocol Controllers (uMCTL2 or uPCTL2) for a complete DDR interface solution.

Key features

  • Low latency, small area, low power
  • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
  • Maximum data rate is process technology dependent
  • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • Compatible with JEDEC standard LPDDR3, DDR3 or DDR3L SDRAMs up to 2,133 Mbps
  • DFI 4.0 Version 2 compliant interface to the memory controller
  • 1:1, 1:2, and 1:4 clock modes supported
  • Optional dual channel DFI for independent 2-channel memories (e.g. LPDDR3/4)
  • Flexible channel architecture
  • Support for two independent LPDDR4 16-bit channels via Synopsys’ unique dual 16-bit PHYs for reduced area and power
  • Support for one DDR4/3 interface
  • Support for 8-bit, 16-bit, 32-bit, and 64-bit wide SDRAMs
  • 8-bit and 16-bit DDR3 and DDR4 supported
  • 16-bit per channel LPDDR4 supported
  • 16-bit and 32-bit per channel LPDDR3 supported
  • Support for three DRAM packaging options:
  • SDRAM components soldered directly to PCB
  • LPDDR3 and LPDDR4 package-on-package (PoP) devices
  • DDR4 and DDR3 UDIMMs and SODIMM
  • 8-bit to 72-bit data path widths in 8-bit increments
  • Partially populated interfaces where allowed by protocol
  • Up to 16 memory ranks with DDR4 3DS devices
  • Flexible configuration options:
  • LPDDR4/LPDDR3: Up to 2 DQ loads, 8 CA loads, and 4 CS loads
  • DDR4/DDR3: Up to 4 DQ loads and 4 ranks of CA loading
  • Shared AC mode that permits one address and command channel to be time division multiplexed between two independent data channels
  • PHY independent, firmware-based training using an embedded calibration processor
  • Utilizes specialized hardware acceleration engines
  • Automatic periodic retraining through the DFI MASTER interface
  • Supports:
  • Command Bus Training (VREFCA)
  • (LPDDR3, LPDDR4) Command Bus eye training relative to CK
  • Write leveling to compensate for CK-DQS timing skew
  • Write training: DQS to DQ
  • Data bus VREFDQ training
  • Read training:
  • DQ bit deskew training
  • DQS to DQ eye centering training using DRAM array
  • IO calibration and ODT calibration
  • Support for up to four distinct trained states/frequencies to permit fast frequency changes
  • Each trained state can have unique frequency and I/O drive and ODT impedance settings
  • Each trained state is maintained across voltage and temperature variation
  • Frequency changes are initiated by the DFI interface without software involvement
  • Multiple inactive idle states:
  • DFI_LP Mode: Most clocks and delay lines gated
  • PHY Inactive: Leakage only
  • PHY Retention: Core power removed, most I/Os powered down, SDRAMs held in self-refresh
  • Voltage and temperature compensated delay lines used for:
  • Centering the clock in the address/command window
  • Centering the strobes in the data eyes
  • Read/write leveling
  • Per-bit deskew on both read and write data paths
  • Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation
  • Only one PLL is required per DDR PHY
  • Integrated PLL bypass to support data rates below 666 Mbps
  • Flexible pre and postamble
  • Support for 1 or 2 clock write preamble
  • Support for static or toggling read preamble of 1 or 2 tCK
  • Support for 0.5 or 1.5 tCK read postamble
  • Software controllable DQ bit and AC bit swizzling
  • Supports PHYs that go around a die corner as well as East-West and North-South orientations
  • Support for 28-nm and below poly orientation rules
  • Includes the PHY Utility Block (PUB)
  • Soft IP Verilog design that includes PHY control features, such as read/write leveling and data eye training
  • APB and TDR interfaces for register access
  • Test support:
  • At-speed loopback testing on both the address and data channels
  • Delay line BIST
  • MUX-scan ATPG (stuck-at SCAN)
  • PLL lock test
  • ZQ calibration test
  • Facilitates a JTAG register interface for easy test access
  • Firmware-based 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and host receivers
  • Direct override programming available for all VREF, ODT, drive strength, and timing delays to facilitate debug and characterization
  • Automotive grade PHYs available featuring AEC-Q100 Grade 2 temperature and ISO 26262 certification

Benefits

  • Supports JEDEC standard LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
  • Support for data rates up to 4,267 Mbps (process dependent)
  • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
  • PHY independent, firmware-based training using an embedded calibration processor
  • Optional dual channel architecture for LPDDR3/4 modes facilitates two independent channels in less area versus two independent PHYs
  • DFI 4.0 version 2 compliant controller interface

Applications

  • Smartphones and tablets
  • Embedded mobile computing
  • Ultraportable laptops/“Ultrabooks”
  • Automotive ADAS and infotainment
  • Mobile multimedia
  • Digital home and office
  • Wireless connectivity

What’s Included?

  • Executable .run installation file includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
  • PUB includes Verilog code, Synthesis/STA constraints and scripts, sample verification environment, and data book
  • Implementation guide, application notes, and quick start manuals
  • Firmware for training, ATE test, and diagnostics
  • DDR PHY compiler
  • Support for PHY emulation
  • Generic DDR PHY FPGA prototyping model available upon request
  • Automotive Grade PHYs include automotive specific deliverables including AEC-Q100 test/characterization report, ISO 26262 safety package (FMEDA, ASIL X ready certificate) and automotive quality documentation (e.g. quality manual, DFMEA analysis report)
  • Optional deliverables include: Signal integrity consulting services; PHY hardening consulting services; Subsystems consulting services

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm Available on request

Specifications

Identity

Part Number
dwc_lpddr4_multiphy_v2_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Standards & Interfaces

Memory
LPDDR4

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about LPDDR IP core

Frequently asked questions about LPDDR Interface IP

What is LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm)?

LPDDR4 multiPHY V2 in TSMC (28nm, 22nm, 16nm, 12nm) is a LPDDR IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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