A/D Converter IP, 10 bits, 10Msps - 50Msps, UMC 0.11um HS/AE process
1.2V/3.3V 10-Bit 10MSPS-50MSPS Pipelined Analog-to-Digital converter with optional power scalable, UMC 0.11um HS/AE Logic process.
- 10 Bit
- UMC
- 110nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
A/D Converter IP, 10 bits, 10Msps - 50Msps, UMC 0.11um HS/AE process
1.2V/3.3V 10-Bit 10MSPS-50MSPS Pipelined Analog-to-Digital converter with optional power scalable, UMC 0.11um HS/AE Logic process.
This IP is gds completed and was verified by simulation.
PCIe 3.1 PHY (6nm, 7nm, 12nm, 14nm, 16nm, 22nm, 28nm and 40nm)
M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
Bandgap reference circuit with high PSRR
SMIC 0.16um process 1.8v/3.3v Generic IO library
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
GLOBALFOUNDRIES 40nm LP 3.3V-2.5/1.1V Power Regulator
This IP is a Low-Dropout (LDO) 3.3V to 2.5V and/or 1.1V power regulator in GLOBALFOUNDRIES 40nm LP 1.1V/2.5V process.
VeriSilicon GSMC 0.18um 1.8v/3v/5v Mult IO for SIMcard
VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple I/O Cell (08) Library developed by VeriSilicon is optimized for Grace Semiconductor Ma…
CMOS Low Power Programmable Frequency Divider(50-2400 MHz)
IP
Poly Phase CMOS Programmable Frequency Divider (50-2400 MHz)
IP
915MHz - 930MHz RPA12C Single stage low power low current PA
IP
The S65LLV25_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifie…
The S65LLV25_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifie…
The S13V33_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifier,…
The S13V33_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifier,…
UFS 3.1 Silicon Proven 2.1 HOST
IP
UFS 3.1 Silicon Proven 2.1 Device, Host
IP
UniPro 2.0 & Silicon Proven v1.8, v1.61
IP
VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Central Semiconductor Manufactur…
The USB1.1 PHY is an IP version of USB transceiver.