Vendor: PRSsemicon Group Category: UFS Controller

UFS 3.1 Silicon Proven 2.1 Device, Host

Key features

  • Compliant with UFS Specification v2.x, 3.x
  • Supports up to 2-lanes (restricted by Standard) running at HS-G3 (5.8Gbps)
  • AXI Support
  • All UPIU Processing
  • Datain, Dataout, Command, Response, RTT, Query, Task Management and Reject
  • Complete control of UIC Layer by UFS Host
  • Error Reporting and Handling Supported
  • Priority arbitration between command, query and task management UPIUs and Indexed based processing within Command and Query UPIUs.
  • Supports 32 UTP Transfer request descriptors and 8 UTP Task Management Descriptors for UFS host
  • Supports Boot LUN, RPMB Well-known LUNs.
  • Device: Up to 8 LUNs configurable. Up to 8 command queue in each LUN. Up to 8 tasks handling for task management.
  • Priority LUN handling.
  • Security Features

Block Diagram

UFS 3.1, 2.1 Device Host block diagram

Specifications

Identity

Part Number
UFS 3.1, 2.1 Device Host
Vendor
PRSsemicon Group
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

PRSsemicon Group
HQ: India

Frequently asked questions about UFS Controller IP

What is UFS 3.1 Silicon Proven 2.1 Device, Host?

UFS 3.1 Silicon Proven 2.1 Device, Host is a UFS Controller IP core from PRSsemicon Group listed on Semi IP Hub.

How should engineers evaluate this UFS Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UFS Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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