Overview
The USB1.1 PHY is an IP version of USB transceiver. It receives data via DP and DM, and transfers data to USB1.1 core via RCV, VM and VP. It is designed in standard logic to interface with the physical layer of Universal Serial Bus. It is capable of transmitting and receiving serial data at either full speed (12M bit/s) or low speed (1.5M bit/s) data rate. The serial interface engine (SIE) controls the state of USB1.1 PHY through the OEN signal. When in receiving mode, it receives data at the output RCV, VM and VP of USB1.1 PHY; when in transmitting mode, it drives the input VPO and VMO of USB1.1 PHY.
This IP is of DUP IO version.
In addition, this IP has the scaled up version (111% scaled-up) of GSMC18RF_USB11_DUP_01B_L which is designed to be used in foundry’s 0.16um (90% shrink) process.
Learn more about Single-Protocol PHY IP core
VeriSilicon today announced its high-performance CPP2000 Camera Post-Processing (CPP) IP, expanding the company’s Image Signal Processing (ISP) solutions with advanced post-processing capabilities.
VeriSilicon today announced that its VC9800D Video Processing Unit (VPU) IP supports AV2 decoding, further expanding the company’s advanced video codec portfolio for next-generation video and streaming applications.
VeriSilicon’s Mature GPU, Display Processing, and DeWarp IPs Collaboratively Enable Highly Integrated, Low-Latency AR Display Processing
These enhanced IPs have successfully achieved ISO 26262 ASIL B functional safety certifications issued by TÜV NORD, an international inspection and certification institution, further validating their suitability and reliability for ADAS and autonomous driving applications.
This IP features an architecture streamlined for seamless SoC integration, delivering high-quality inference with low power consumption and a compact silicon footprint. The certificate was issued by SGS-TÜV Saar, an international testing, inspection and certification institution.
The Coral NPU is built on the open RISC-V instruction set architecture, featuring native tensor processing capabilities, supporting mainstream machine learning frameworks such as JAX, PyTorch, and TensorFlow Lite (TFLite), and utilizing open-standard tools like Multi-Level Intermediate Representation (MLIR) from the Low Level Virtual Machine (LLVM) project for compiler infrastructure.
