Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Analog

CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.

VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Central Semiconductor Manufactur…

Overview

VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Central Semiconductor Manufacturing Corporation (CSMC) 0.13μm Logic 1P8M Salicide 1.2/3.3V process. This library supports Device Under Pad (DUP).
This library includes analog I/O cells and digital I/O cells. The digital I/O cells can take 5V tolerance and work with configurable and variable driving strength between 2mA - 24mA. Its maximum rating frequency is 200MHz, but the actual frequency depends on loading, system timing requirement and selected IO driver strength.
This library supports Inline DUP I/O pad.

Key features

  • VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library supports design with six, seven or eight layers of metal.

Specifications

Identity

Part Number
CS13V33_DUPIO_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Frequently asked questions about Analog I/O Pad Library IP cores

What is CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.?

CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad. is a Analog IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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