MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and …
- TSMC
- 28nm
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MIPI D-PHY RX/TX v1.1 / v1.2 IP in TSMC (12/16nm, 28nm, 40nm, and 55nm process)
The D-PHY is a popular MIPI physical layer developed for mobile applications because it is a flexible, high-speed, low-power and …
One Port Register File Compiler IP, UMC 28nm HPC process
UMC 28nm HPC process One Port Register File
SMIC 0.16um LL process 1.8v/3.3v Generic IO library
IP
Small footprint vector graphics for IoT
IP
SMIC 65nm LL(HVt) ECO cells compatible with VHS standard cell library.
SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
IP
SMIC 65nm LL Standard digital and oscillator IO
IP
SMIC 65nm LL Standard analog IO
IP
SMIC 65nm LL Standard digital and oscillator IO
IP
SMIC 65nm LL Standard analog IO
IP
SMIC 55nm LL(HVt) ECO cells compatible with HS standard cell library.
SMIC 55nm LL LPDDR interface for DRAM application
IP
SMIC 55nm LL Standard digital and oscillator IO
IP
SMIC 55nm LL Standard digital, analog and oscillator IO
IP
SMIC 55nm LL Multi-voltage programmable digital IO
IP
SMIC 0.13um Generic UHD RVT Logic standard cell library.
SMIC 0.13um LL low power single port SRAM .
0.13um LL low power single port SRAM .
SMIC 0.13um LL low power Dual port SRAM.
0.13um LL low power Dual port SRAM.