M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
- USB 1.1
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
USB2.0 Dual-Role PHY, HLMC 40LP
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LFR6LP
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LF6S
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, Samsung LF6
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
10-bit 1Msps Asynchronous SAR ADC
10-bit 1Msps Asynchronous SAR ADC
RISC-V Vector Extension
RISC-V Real-time Processor
RISC-V High Performance Processor
RISC-V High Performance Processor
Gen7 supports 128Gbps and backward compatible with previous versions of PCIE.
An interconnect component connects initiators and targets in a system.
The bus converter module transforms 64-bit wide initiator data buses to smaller 32-bit target data buses or vice-versa.
Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely a…
Decoder logic controls numerous targets based on input from the initiator.
IP
The FPGA Lock is a small FPGA IP core that uses the $0.52 Microchip ATSHA204A hardened crypto authentication IC and one FPGA pin …
The pervasive nature of Ethernet has made it an integral part of our connected world, driving communication speeds up to 1.6T.
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process
RISC-V IP - Dual Issue Power Efficient Application
Dual Issue Power Efficient Application Core - VisionL is a dual-issue power-efficient application core designed for applications …
RISC-V IP - Dual Issue Embedded Application
Dual Issue Embedded Application Core - VisionG is a dual-issue embedded application core, providing high-performance computing ca…