Overview
The pervasive nature of Ethernet has made it an integral part of our connected world, driving communication speeds up to 1.6T. To meet the quality, high-performance, and security demands of Ethernet SoCs, Synopsys delivers a complete IP solution consisting of configurable MAC & PCS controllers and silicon-proven 1G to 224G PHYs, MACsec security modules, verification IP, and Interface IP Subsystems. Synopsys provides routing feasibility studies, package substrate guidelines, signal and power integrity models, and thorough crosstalk analysis to help you achieve first-pass silicon success. With the complete Ethernet IP solution, which has undergone extensive third-party interoperability testing and automotive qualification, SoC designers can accelerate time-to-market and reduce integration risk for HPC, IoT, automotive, and networking SoCs.
Learn more about Ethernet IP core
Learn how ESUN enhances Ethernet for lossless, predictable AI scale-up networking—cutting overhead, reducing tail latency, and improving efficiency.
Ultra Ethernet, designed for scale out architectures, is an open, interoperable, high-performance protocol solution tailored for AI, supported by industry leaders across switch, networking, semiconductor, and system providers, as well as hyperscalers.
Synopsys and TeraSignal have reached two milestones in optical networking, demonstrating seamless interoperability for PCIe 6.x and 112 Gbps Ethernet over linear optics. These industry-first achievements highlight the potential of linear optics to transform data transmission in hyperscale data centers and high-performance computing (HPC) environments.
Without Ethernet connectivity, modern computing would be vastly different. “Ethernet underlies nearly everything in tech,” says Kent Lusted, a Synopsys distinguished architect who has spent the past 14 years helping shape the technology as a leader of and contributor to Ethernet standards groups.
This article delves into the technical aspects of how scaling up and out is becoming a critical need for HPC and AI chip developers, and how new standards such as Ultra Ethernet and Ultra Accelerator Link (UALink) aim to tackle the challenges of high-bandwidth, low-latency connectivity and efficient resource management.
This article explores how integrating multi-die designs with PCIe & Ethernet, in conjunction with UCIe IP, maximizes bandwidth and performance, facilitating the scaling up and out of modern AI data center infrastructures.