UHF Passive RFID Front-End - EPCGlobal Class 1 Gen 2/ISO18000-6C Compliant
This macro-cell is an ultra low power analog/RF front-end core designed for SilTerra 0.18μm CMOS technology.
- RF Front End
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UHF Passive RFID Front-End - EPCGlobal Class 1 Gen 2/ISO18000-6C Compliant
This macro-cell is an ultra low power analog/RF front-end core designed for SilTerra 0.18μm CMOS technology.
Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm CL160G CMOS technology.
The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed commun…
Nand Flash write cycles are limited.
The DDR5MRDIMM2 VIP is fully compliant with Standard JEDEC Specifications.
AHB/AXI/Wishbone DMA Controller
The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, wh…
General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
xSPI (Expanded Serial Peripheral Interface) Verification IP
xSPI (Expanded Serial Peripheral Interface) is the serial synchronous communication protocol developed by JEDEC eXpanded Serial P…
XMBus(Extended Management Bus) Verification IP provides an smart way to verify the XMBus bi-directional two-wire bus.
XLGMII 40G Ethernet Verification IP
The XLGMII 40G Ethernet Verification IP is compliant with IEEE 802.3ba specifications and verifies MAC-to-PHY layer interfaces of…
10G XAUI/10GBase-KX4 Ethernet Verification IP
The 10G XAUI/10GBase-KX4 Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer inter…
10G TBI (PCS) Ethernet Verification IP
The 10G TBI Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of desi…
10G 64b/66b WIS Ethernet Verification IP
The 10G 64b/66b WIS Ethernet Verification IP is compliant with IEEE 802.3ae specifications and verifies MAC-to-PHY layer interfac…
10GBase-KR Ethernet Verification IP
The 10GBase-KR Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of d…
XGMII Ethernet Verification IP
The 10G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs …
OpenCores Wishbone B3 Verification IP
OpenCores Wishbone B3 Verification IP provides an smart way to verify the OpenCores Wishbone B3 component of a SOC or a ASIC.
V-By-One HS is the serial communication protocol developed by Thine Electronics, Inc to support the higher frame rates and the hi…
USIM Verification IP is a smart way to verify the USIM component of a SOC or ASIC.
USB TYPE-C Verification IP provides an smart way to verify the USB TYPE-C.
USB Power Delivery Verification IP provides an smart way to verify the USB Power Delivery.