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Imec and Diraq today announce they have demonstrated the coherent operation and readout of an eight silicon MOS spin-qubit array designed and fabricated on imec's advanced 300mm spin-qubit technology platform using a CMOS-compatible process.
Ferroelectric capacitors are shown to enable low-voltage (~1.3 V) operation through ferroelectric layer scaling while maintaining high remnant polarization (>40 μC/cm²) and endurance (≥10¹³ cycles), key requirements for DRAM-like memory applications.
For the first time, scaled nFETs (implementing MoS2 as the channel material) and pFETs (either WS2 or WSe2-based) with 50nm contacted poly pitch (CPP) could be demonstrated, with good current-voltage characteristics.
Building on this, imec further demonstrates the first full transceiver architecture compliant with IEEE 802.15.4ab, delivering up to a 32x improvement in ranging performance through combined receiver, transmitter, and IEEE 802.15.4ab standard innovations
The feasibility of processing a charge coupled device (CCD) in a 3D NAND-like architecture paves the way for a cost-effective, high-bit-density memory solution to address the memory wall for AI specific workloads
