SMIC 0.11um 7 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 7T HVT High-Density Standard Cell Library
- SMIC
- 110nm
- G
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SMIC 0.11um 7 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 7T HVT High-Density Standard Cell Library
SMIC 0.11um 7 track High Density Standard Cell Library - RVT,1.2v operating voltage
SMIC 0.11um 7T RVT High-Density Standard Cell Library
SMIC 0.11um 6 track High Density Standard Cell Library - LVT,1.2v operating voltage
SMIC 0.11um 6T LVT High-Density Standard Cell Library
SMIC 0.11um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 6T HVT High-Density Standard Cell Library
SMIC 0.11um 6 track High Density Standard Cell Library - RVT,1.2v operating voltage
SMIC 0.11um 6T RVT High-Density Standard Cell Library
SMIC 0.11um 9 track Standard Cell Library - LVT,1.2v operating voltage
SMIC 0.11um 9 track High Density Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 9 track Standard Cell Library - HVT,1.2v operating voltage
SMIC 0.11um 9 track High Density Standard Cell Library - RVT, 1.2v operating voltage
SMIC 0.11um 9T RVT High-Density Standard Cell Library
SMIC 90nm Power Management Kit, 1.2v operating voltage
SMIC 90nm Power Management Kit Library
16-bit -90dB THD+N Multi-Channel Audio Sample Rate Converter
The ASRC-lite (CWda50) is part of Coreworks family of multi-channel asynchronous Audio Sample Rate Converter (ASRC).
256-bit SHA Secure Hash Crypto Engine
The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256.
Message Digest Algorithm Processor
The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P, AES-CCM and AES-GCM cores.
AES-CCM Authenticated Encrypt/Decrypt Engine
The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
AES-GCM Authenticated Encrypt/Decrypt Engine
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Programmable Advanced Encryption Standard Engine
The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Advanced Encryption Standard Engine
The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Ultra-Fast Baseline and Extended JPEG Decoder
This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 sta…
Baseline and Extended JPEG Decoder
The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Exten…
This JPEG decompression IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard.