Phase Locked Loop (PLL) Module
Xilinx, Inc.
•
HQ:
USA
The Phase Locked Loop primitive in Virtex-5 FXT parts is used to generate multiple clocks with defined phase and frequency relati…
- PLL
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MIPI DSI TX Controller Subsystem
Xilinx, Inc.• HQ: USAThe Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) ba…
- MIPI
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MIPI CSI Controller Subsystems
Xilinx, Inc.• HQ: USAThe Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (…
- MIPI
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MicroBlaze Microcontroller Reference Design
Xilinx, Inc.• HQ: USAMicroBlaze™ is a 32-bit RISC soft processor core that can be used with soft peripherals to design embedded systems in Xilinx FPGA…
- MCU
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Xilinx, Inc.• HQ: USA
The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Seri…
- Test / Debug
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Hard-core Tri-mode Ethernet MAC
Xilinx, Inc.• HQ: USAThe HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.
- Ethernet
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Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…
- Protocol Bridge
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Xilinx, Inc.• HQ: USA
The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cos…
- Controller
- DDR4
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Xilinx, Inc.• HQ: USA
The Xilinx DDR3 controller is high performance (2133Mbps in UItraScale) with support for lower power DDR3L as well as UDIMMs, SOD…
- Controller
- DDR3
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Xilinx, Inc.• HQ: USA
Xilinx provided utility function to simplify design in Vivado IP Integrator.
- Control Logic
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Xilinx, Inc.• HQ: USA
Xilinx provided utility function to simplify design in Vivado IP Integrator.
- Control Logic
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ChipScope Pro (IBERT) for Virtex-6 GTH
Xilinx, Inc.• HQ: USAThe LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
- Test / Debug
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CAN with Flexible Data Rate (CAN FD)
Xilinx, Inc.• HQ: USAThe Xilinx® CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control…
- CAN / CAN-FD / CAN-XL
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Xilinx, Inc.• HQ: USA
The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible prod…
- Protocol Bridge
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Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…
- Network-On-Chip
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Xilinx, Inc.• HQ: USA
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
- PCI Express
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Xilinx, Inc.• HQ: USA
The AXI MCDMA facilitates large data migration, offloading the task from the embedded processor.
- DMA
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Xilinx, Inc.• HQ: USA
The Xilinx® LogiCORE™ AXI AMM Bridge IP core connects Avalon bridge slave IPs with AXI interface masters.
- Protocol Bridge
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7 Series Integrated Block for PCI Express (PCIe)
Xilinx, Inc.• HQ: USAXilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
- PCI Express
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64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
Xilinx, Inc.• HQ: USADO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
- PCI