UltraScale / UltraScale+ Interlaken
The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect proto…
- Interlaken
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UltraScale / UltraScale+ Interlaken
The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect proto…
System Integrated Logic Analyzer (System ILA)
The customizable System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer which can be used to monitor the inter…
Xilinx provided utility function to simplify design in Vivado IP Integrator.
The RLD3 Controller gives you the ability to design for Reduced Latency DRAM while maintaining high performance and density.
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.
This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge.
Phase Locked Loop (PLL) Module
The Phase Locked Loop primitive in Virtex-5 FXT parts is used to generate multiple clocks with defined phase and frequency relati…
MIPI DSI TX Controller Subsystem
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) ba…
MIPI CSI Controller Subsystems
The Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (…
MicroBlaze Microcontroller Reference Design
MicroBlaze™ is a 32-bit RISC soft processor core that can be used with soft peripherals to design embedded systems in Xilinx FPGA…
The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Seri…
Hard-core Tri-mode Ethernet MAC
The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…
The Xilinx DDR4 controller is high performance (2667Mbps in UItraScale+) and supports a wide range of configurations from low cos…
The Xilinx DDR3 controller is high performance (2133Mbps in UItraScale) with support for lower power DDR3L as well as UDIMMs, SOD…
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
ChipScope Pro (IBERT) for Virtex-6 GTH
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
CAN with Flexible Data Rate (CAN FD)
The Xilinx® CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control…
The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible prod…