Xilinx, Inc.
•
HQ:
USA
Reset Verification IP can be used to generate reset signals in testbench.
- Verification IP
Compare 18,292 Semiconductor IP Cores from 472 vendors
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Zynq UltraScale+ RFSoC RF Data Converter
Xilinx, Inc.• HQ: USAThe Xilinx® Zynq® UltraScale+™ RFSoC family integrates the key subsystems required to implement a software-defined radio includin…
- ADC
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Xilinx, Inc.• HQ: USA
Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
- SRAM
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Partial Reconfiguration Bitstream Monitor IP
Xilinx, Inc.• HQ: USAThe Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design.
- Monitoring
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Partial Reconfiguration AXI Shutdown Manager IP
Xilinx, Inc.• HQ: USAThe Partial Reconfiguration (PR) AXI Shutdown Manager can be used to make the AXI interfaces between a Reconfigurable Partition a…
- System Controller
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QDMA Subsystem for PCI Express
Xilinx, Inc.• HQ: USAThe Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with th…
- PCI Express
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Xilinx, Inc.• HQ: USA
The LPDDR3 Controller gives you the ability to design with less power and a smaller form factor while maintaining high performanc…
- Controller
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Xilinx, Inc.• HQ: USA
Massive memory bandwidth, the simplicity of an AXI Interface, no need for external pins HBM IP, made available for Virtex UltraSc…
- Controller
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Xilinx, Inc.• HQ: USA
The ETRNIC (Xilinx Embedded Target RDMA enabled NIC) IP is a target only implementation of RDMA over Converged Ethernet (RoCE v2)…
- Ethernet
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Xilinx, Inc.• HQ: USA
Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…
- Interlaken
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Xilinx, Inc.• HQ: USA
The 400G High Speed Ethernet (400G HSEC) Subsystem provides the 400G Ethernet Media Access Control (MAC) with a Physical Coding S…
- Ethernet
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Xilinx, Inc.• HQ: USA
The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with…
- Ethernet
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Xilinx, Inc.• HQ: USA
The Polar Encoder/Decoder soft IP core supports Polar encoding and decoding.
- Channel Coding
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Xilinx, Inc.• HQ: USA
Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data tran…
- Channel Coding
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Xilinx, Inc.• HQ: USA
The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …
- Channel Coding
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Xilinx, Inc.• HQ: USA
The Xilinx® 10G Ethernet TSN solution provides a 10 Gigabit per second (Gbps) Ethernet Media Access Controller integrated with a …
- Ethernet
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25G IEEE 802.3by Reed-Solomon Forward Error Correction
Xilinx, Inc.• HQ: USAXilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise …
- Channel Coding
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AXI Bus Functional Model (BFM)
Xilinx, Inc.• HQ: USAThe ability to purchase AXI BFM has been discontinued as of December 1, 2016.
- Protocol Bridge
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Xilinx, Inc.• HQ: USA
Clock Verification IP can be used to generate clock signals in testbench.
- Verification IP
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ChipScope Pro (IBERT) for Virtex-6 FPGA GTH
Xilinx, Inc.• HQ: USAThe LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
- Test / Debug