Build low cost, efficient AI solutions in a wide range of embedded devices with Arm’s latest addition to the Ethos-U microNPU fam…
- Edge AI Accelerator
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Build low cost, efficient AI solutions in a wide range of embedded devices with Arm’s latest addition to the Ethos-U microNPU fam…
IMG B-Series takes all of the advances of IMG A-Series, the fastest GPU IP ever created, and offers new configurations with even …
The TSN-SW implements a flexible, low-latency, multiport TSN Ethernet switch.
The Universal Asynchronous Receiver/Transmitter (UART) is a hardware device that translates data between parallel and serial form…
The SPI Slave IP Core implements an SPI Slave fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
The SPI Master IP Core implements an SPI Master fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
SDRAM Controller DO-254 IP Core
The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as…
The I2C Slave IP Core implements an I2C Slave fully compliant to the I2C-bus specification and user manual Rev.
The I2C Master IP Core implements an I2C Master fully compliant to the I2C-bus specification and user manual Rev.
ARINC 429 Transmitter DO-254 IP Core
The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.
MIL-STD-1553C Remote Terminal DO-254 IP Core
The MIL_1553 RT IP Core implements a Remote Terminal as specified in the MIL-STD-1553C specification.
ARINC 429 Receiver DO-254 IP Core
The ARINC 429 Rx IP Core implements a receiver as specified in the ARINC Specification 429 Part 1-17.
10/100/1000 Ethernet MAC DO-254 IP Core
The 10/100/1000 Ethernet MAC Controller DO-254 IP Core implements the Media Access Control as specified in the IEEE 802.3-2008 sp…
The CAN Controller implements a Controller Area Network as specified in the ISO 11898 Part 1 and in the CAN Specification Version…
First High-Performance GPU with Functional Safety
The Mali-G78AE GPU has been designed to address the complex requirements of autonomous use cases, bringing features to fulfill th…
Image Signal Processing for Automotive and Industrial Applications
Mali-C71AE is Arm’s highest performance image signal processor (ISP) developed for the emerging smart automotive systems and indu…
Highest Performance CPU with Split-Lock
Cortex-A78AE is the highest performance Cortex-A processor designed for devices undertaking complex and demanding safety-critical…
U54 MC Multicore: four U54 cores and one S51 core
The SiFive U54-MC Standard Core is the world's first RISC-V application processor, capable of supporting full-featured operating …
U54 Linux-capable RISC V application processor
The SiFive U54 Standard Core is a single-core instantiation of the world's first RISC-V application processor, capable of support…
E76-MC Quad-core 32-bit embedded processor
The SiFive E76-MC Standard Core is a high-performance quad-core 32-bit embedded processor which is fully-compliant with the RISC-…