112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
- Multi-Protocol PHY
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
112G VSR PHY, TSMC N5 x8, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
UCIe Controller baseline for Streaming Protocols
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
512x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V CMOS 18B Process
The ATO00512X1MX180LB52ND is organized as a 512-bit by 1 one-time programmable (OTP).
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
112G PHY, TSMC N5 x2, North/South (vertical) poly orientation
The Multi-Protocol 112G PHY IP is part of a high performance multi-rate transceiver portfolio for high-end networking and high pe…
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.
LPDDR5X/5/4X PHY - SS SF5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
The NB-IoT NTN System Test Bench (STB) is a cost-effective, flexible testing environment for NB-IoT NTN eNodeB product developers.
Two-Digit Nanosecond PCIe 7.0-CXL 4.0 Link Controller IP
The PCIe PHY IP supports PCIe Gen 4.0, 5.0, and 6.0, and is validated through interoperability testing in collaboration with glob…
MIL-STD-1553B is a military specification for a Digital Time Division Command/Response Data Bus, featuring half-duplex, Mancheste…
LPDDR Controller ASIL B Compliant supporting LPDDR5, LPDDR4 and LPDDR4X for Automotive Applications
The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
LPDDR Controller ASIL B Compliant supporting LPDDR5X, LPDDR5 and LPDDR4X for Automotive Applications
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
The GenAI IP is the smallest version of our NPU, tailored to small devices such as FPGAs and Adaptive SoCs, where the maximum Fre…
The DP and eDP TX/RX PHY IP provides a compact, low-power solution for high-speed external display interfaces.
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and ot…
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs.
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semicondu…
Peripheral Bus (APB) is one of the Microcontroller Bus Architecture (AMBA) family protocols.