The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…
- Displayport
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…
Unified Architecture for Cutting-Edge Intelligence
Multi-channel DVB-C / J83 FEC encoder
The CMS0044 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified b…
The CMS0045 ISDB-T Modulator provides all the necessary processing steps to modulate one, two or three transport stream into a co…
The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X wide-band dig…
The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.
The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.
The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal…
The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Configurable RISC-V processor IP core
The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.
Built on the success of Helion's industry proven cryptographic IP cores, the Helion ESP Engine provides hardware acceleration of …
Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVC VIP is fully documented,off-the-shelf component for the Developers …
USB 2.0 VMM System Verilog VIP
The USB 2.0 VMM SystemVerilog VIP is fully documented, off the shelf component for the verification of the USB 2.0 compliant Func…
The 1394 OVC is a fully documented, off-the-shelf component using the Open Verification Methodology for quickly enabling function…
UART eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment.
USB OVA - USB 2.0 Function Controller OVA Checker IP
USB 2.0 Function Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the USB 2.0 complia…
The USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant Function Cont…
The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect va…
The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suita…
The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - …