The APB Timer module is a sixteen-bit down counter with a selectable prescaler.
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The APB Timer module is a sixteen-bit down counter with a selectable prescaler.
The Real Time Clock (RTC) is a clock-calendar IP core that keeps track of the “Time of Day”.
The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal.
APB General Purpose IO (w/ interrupt)
The APB GPIO is a configurable module allowing the use of up to 32 scalable I/O lines.
The AHB TFT LCD Controller is a configurable core that interfaces to an AHB microprocessor bus and provides all the timing contro…
The interrupt controller monitors interrupts from all other modules within the system and issues interrupt requests to the proces…
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…
The AHB Arbiter arbitrates for the AHB bus among as many as four AHB master components.
The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction.
13 bits 2.56MS/s SAR ADC - TowerJazz 0.18um
13 bits 2.56MS/s successive approximation ADC.
Tiny Area High Performance Microcontroller
The DT8051 is an area optimized, tiny soft core of a single-chip 8-bit embedded microcontroller, based on the World's fastest and…
The HSCAN IP is a high speed CAN Transceiver for automotive 12V applications.
The 60 GHz PA is a power amplifier designed for applications in the 57 – 64 GHz frequency range.
The 60 GHz LNA is a low noise amplifier designed for applications in the 57 – 64 GHz frequency range.
This hardware IP core features a full Secure Hash Algorithm SHA1.
USB4.0 router, Certified USB 5G/10G and 20G Device controller
USB 5G,10G, 20G and 4.0 Device router controller is a configurable core and implements the USB device functionality and can be in…
Digital I/Q Imbalance correction IP for Wireless Applications
The IQE 100 is a wideband imbalance correction IP, that digitally match in-phase and quadrature signal paths in radio architectur…
This hardware IP core is a ZBT SRAM controller capable of automatically managing single address and full continuous burst read/wr…
This IP core features a full-hardware sound compressor using the algorithm IMA ADPCM.
Bilinear Bayer to RGB converter for Image Sensors
This hardware IP core features a high speed and quality Bilinear Bayer to RGB converter.