10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
- Channel Coding
- Silicon proven
- Now
- ITU-T G.975.1 (super-FEC fo…
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
Brite provides USB2.0 OTG PHY which is a mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (So…
RF I/O Pad Set and Discrete RF ESD Protection Components
The RF library include analog signal pads and ESD protection components for RF applications.
Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
The UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a flexible and c…
95 dB of SNR, 24-bit audio CODEC with headphone output and line-out
SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording perform…
RTP/UDP/IP Protocol Hardware Stack – Raw, Uncompressed RGB/YUV Video Streams Packet Processing
The DB-RTP-UDP-IP Intellectual Property Core is an RTP/UDP/IP Protocol Hardware Stack with the following protocol processing unit…
I2C Controller IP – Slave, User Register Interface, No CPU Required
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal conf…
Half Precision IEEE-754R complete FPU for graphics processing
The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for…
Asynchronous FIFO with configurable flags and counts
The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.
Synchronous FIFO with configurable flags and counts
The sFIFO controls are designed to operate over a wide range of clock frequencies.
CCSDS (8160,7136) LDPC Decoder
The LCD01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control decoder.
CCSDS (8160,7136) LDPC Encoder
The LCE01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control encoder.
The CRYPT-IP-120 combines local key storage, an AES cipher (AES-IP-39), a SHA-2 hash (HASH-IP-57) and DMA capability into an easy…
The ZUC-IP-48 (EIP-48) cipher accelerators implement the specification of the 3GPP Confidentiality and Integrity Algorithms as sp…
High Profiles H.264 Encoder − High 10, High 4:2:2 and High 4:4:4 (12-bit 4:2:2 or 4:2:0) Profiles
The H264-HP-E core is an and self-contained ITU-T H.264 High profiles hardware encoder.
Baseline Profile H.264 Encoder
The H264-BP-E core is an self-contained hardware H.264 encoder that conforms to the ITU-T H.264 Constrained Baseline Profile.
Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder
The UHT-JPEG-D core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed t…
Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
The UHT-JPEG-E core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG encoder, with optio…
AES Encryption & Decryption IP Core − Programmable Block Cipher Modes
The AES-P IP core implements the FIPS-197 Encryption Standard.
SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators
The HASH-IP-57 (EIP-57) is IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2…