ULP 32.768kHz oscillator in Silterra 0.18 um
This macro-cell is an ultra-low power, general purpose 32.768kHz internal oscillator core aimed for RTC (real time clock) applica…
- Silterra
- 180nm
- G
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
ULP 32.768kHz oscillator in Silterra 0.18 um
This macro-cell is an ultra-low power, general purpose 32.768kHz internal oscillator core aimed for RTC (real time clock) applica…
USB 3.1 is the most recent version of the USB (Universal Serial Bus) standard for connecting electronic devices in host and devic…
Serial Front Panel Data Port Gen3
Serial Front Panel Data Port Gen3 is a next-generation, high bandwidth serial communications protocol defined by the ANSI/VITA 17…
1G IP/UDP full HW Stack Transmitter / Receiver
To efficient transfer large amount of data and off-load the system processor, BitSim has launched its IP, Bit-UDP Ethernet.
OT3910bj is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to poi…
600Mb/s Authentication IP Core for AXI-4 Streams Optimized for Area MD5 Stream Authentication IP Cores converts streams of data i…
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …
LEE Flash ZT (ZT) achieves automotive grade temperature and quality grade.
sROMet compiler - TSMC 40 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler r…
Audio ADC with 100 dB Dynamic Range, 24-bit six channel with embedded VAD
The YANZI-A-hexADC-VD.01 is a feature-rich audio ADC which provides the insurance of the best sound quality after integration int…
Dolphin Design high-fidelity audio CODEC, sCODa95-H1-LR-D.04 combines a set of audio features and a small silicon footprint with …
Low frequency XTAL oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of clocks.
Low frequency XTAL oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of clocks.
Low frequency 32-kHz RC oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of voltage regulators and clocks.
IEEE 802.3cg® 10BASE-T1S Digital Controller
The CT25205 Digital IP core provides the PMA, PCS, and PLCA Reconciliation Sublayer building blocks of a standard IEEE 802.3cg® 1…
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
The VPC-6 is a linear frame rate converter used to convert between frame rates while maintaining the appearance of smooth motion.
AHB DES and Triple DES with DMA
The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus.