AHB DES and Triple DES with DMA
The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus.
Overview
The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. The Controller encrypts or decrypts blocks of data based on the DES encryption standard. In order to accommodate a wide variety of system requirements, the Engine can be generated in two modes: LowLatency and LowGateCount. For a TDES system, three DES cores are instantiated.
Key features
- AHB Master component DMA
- AHB Slave component Register Interface
- DES/TDES modes supported:
- Electronic Code Book (ECB)
- Cipher Block Chaining (CBC)
- Output Feedback (OF)
- Maskable Interrupt
Block Diagram
What’s Included?
- Verilog Source
- Complete Test Environment
- AHB Bus Functional Model
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Symmetric Crypto IP core
CXL - The Latest Specification in Secured Network Traffic
Securing your apps with Public Key Cryptography & Digital Signature
The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era
RoT: The Foundation of Security
Tailoring Root Of Trust Security Capabilities To Specific Customer Needs
Frequently asked questions about Symmetric Cryptography IP cores
What is AHB DES and Triple DES with DMA?
AHB DES and Triple DES with DMA is a Symmetric Crypto IP core from Silvaco, Inc. listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.