Analog Bits IP Listing

The Scalable LDO (Low Drop Out) Regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully …

• TSMC
• 3nm
• N3P

The Scalable LDO (Low Drop Out) Regulator macro addresses typical SOC power supply and other voltage regulation needs in a fully …

• TSMC
• 3nm
• N3E

The Jitter Cleaning PLL macro is implemented in Analog Bits’ proprietary architecture that uses 0.9V core and 1.8V IO oxide devic…

• TSMC
• 40nm
• G

The Integrated Bandgap and Programmable Current Reference macro comprehensively addresses typical SOC voltage and current referen…

• TSMC
• 7nm
• N7FF

The Integrated Bandgap with Dual Voltage Outputs macro comprehensively addresses typical SOC voltage reference needs in a fully i…

• TSMC
• 6nm
• N6FF

The Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macr…

• TSMC
• 3nm
• N3P

The Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macr…

• TSMC
• 3nm
• N3E

The Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a fully integrated easy-to-use macr…

• TSMC
• 2nm
• N2P

The high speed wide range PLL addresses markets and applications that demand very low power and optimized for area efficiencies.

• GlobalFoundries
• 65nm
• G

The High Speed PLL creates a high-speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 6nm
• N6FF

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 7nm
• N7FF

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 6nm
• N6FF

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 7nm
• N7FF

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 6nm
• N6FF

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 5nm
• N5A

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 5nm
• N5

The High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

• TSMC
• 4nm
• N4P

The High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source…

• TSMC
• 3nm
• N3P

The High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source…

• TSMC
• 3nm
• N3E

The High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source…

• TSMC
• 2nm
• N2P