Vendor: Analog Bits Inc. Category: PLL

High Performance 20GHz C2C PLL on TSMC CLN3E

The High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source…

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TSMC 3nm N3E View all specifications

Overview

The High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous interfaces and other high speed logic applications. The PLL is designed in a standard digital logic process and uses robust design techniques including an integrated LDO (Low Drop Out regulator) to work in typical SoC environments.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.2V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 100 MHz VCO Frequency FVCO 10000 20000 MHz Output Frequency FOUT 2500 10000 MHz Output Duty Cycle tDO -2 2 ps Lock Time tLOCK 70 µs Reset Time tRESET 1 µs 600fs-RMS @10GHz (with integration band Long Term Random Jitter RJ from 1GHz to Nyquist) Total area of macro A 0.018 sq.mm Dimensions: 120.105um (X) by 147.196um (H) Total Power (unloaded) IDD 14 mW Output Load CL 50 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.08 1.2 1.32 V Operational Temperature TOP -40 25 125 C

Key features

  • Electrically Programmable PLL for multiple applications
  • Wide Ranges of Output Frequency for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Integrated LDO to reduce deterministic jitter
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection
  • CML output optionally available

Silicon Options

Foundry Node Process Maturity
TSMC 3nm N3E —

Specifications

Identity

Part Number
High Performance 20GHz C2C PLL on TSMC CLN3E
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Analog Bits Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is High Performance 20GHz C2C PLL on TSMC CLN3E?

High Performance 20GHz C2C PLL on TSMC CLN3E is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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