Vendor: Analog Bits Inc. Category: PLL

High Speed Multi-Phase PLL on TSMC CLN6FF

The High Speed PLL creates a high-speed clock with good duty cycle and jitter characteristics useful for high speed, source synch…

TSMC 6nm N6FF View all specifications

Overview

The High Speed PLL creates a high-speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous interfaces and other high speed logic applications. The PLL is designed in a standard digital logic process and uses robust design techniques including an integrated LDO (Low Drop Out regulator) to work in typical SoC environments.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 100 MHz VCO Frequency FVCO 10000 20000 MHz Output Frequency FOUT 2500 5000 MHz Output Duty Cycle tDO 48 52 % Lock Time tLOCK 70 µs Reset Time tRESET 1 µs 600fs-RMS @4GHz (with integration band Long Term Random Jitter RJ from 1GHz to Nyquist) Total area of macro A 0.012 sq.mm Dimensions: 117um (X) by 100um (H) Total Power (unloaded) IDD 14 mW Output Load CL 50 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V Operational Temperature TOP -40 25 125 C

Key features

  • Electrically Programmable PLL for multiple applications
  • Wide Ranges of Output Frequency for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection
  • 4-phase output clocks (separated by 90 degrees)

Silicon Options

Foundry Node Process Maturity
TSMC 6nm N6FF —

Specifications

Identity

Part Number
High Speed Multi-Phase PLL on TSMC CLN6FF
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Analog Bits to Participate in a Customer Test Chip Tapeout on TSMC A14 and Present Papers with Cerebras, Arm and Socionext on Real-Time On-Chip Power Sensing and Delivery at 2026 TSMC Global OIP Ecosystem Events

At TSMC 2026 North America OIP Ecosystem Forum, Analog Bits will showcase new real-time power observability and sensing analog IP in TSMC’s N2P process technology and present a paper with Cerebras; Papers planned with partners at global OIP Ecosystem events to highlight smarter power delivery for scalable SoCs targeting data centers, automotive and more.

Frequently asked questions about PLL IP cores

What is High Speed Multi-Phase PLL on TSMC CLN6FF?

High Speed Multi-Phase PLL on TSMC CLN6FF is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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