USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
- USB 2.0
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
External NOR flash protection solution that supports real-time decryption and execution in place
The Flash Protection Series is a suite of enhancements available for PUFcc and PUFrt, extending the Hardware Root of Trust to pro…
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization.
External NAND flash protection, designed to secure stored assets with a local key from PUF
The Flash Protection Series is a suite of enhancements available for PUFcc and PUFrt, extending the Hardware Root of Trust to pro…
QOI Lossless Image Compression Encoder
The QOIE Core is an encoder that implements a efficient, low-power, lossless image compression engine compliant with the Quite OK…
The LCE02C is a high speed encoder for the CCSDS telemetry (TM) accumulate, repeat by four, jagged accumulate (AR4JA) low density…
Combined Power-On-Reset and Brown-Out-Reset in SMIC 40EF
Combined Power-On-Reset and Brown-Out-Reset in SMIC 40EF
Over-voltage Protection Module to handle direct connection of voltage regulators to a 5V battery using standard 2.5 OD 3.3V devic…
Roviero has developed a natively graph computing processor for edge inference.
1.8V General Purpose I/O Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev.
3.3V 100MHz Oscillator IO Inline Pad Set
The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell.
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core po…
The SD library provides the driver / receiver cell and required support cells for SD 3.0 signaling.
IPMX is the emerging AV over IP standard for use in Professional AV.
The MIPS® P8700 Multiprocessing System is the first RV64GCZba_Zbb compliant CPU IP focused on high performance, data movement and…
The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP p…
QOI Image Decompressor IP Core
This core implements the QOI lossless image compression algorithm decompressing QOI header-less files and producing RGB 24 bits p…
This core implements the QOI lossless image compression algorithm producing a raw, header-less file.
VISENGI's SHA-2 Secure Hash Algorithm IP core has been developed to be the highest throughput SHA-2 cryptographic hasher while at…